1. Field of the Invention
The present invention relates to a wiring substrate, a manufacturing method thereof and a semiconductor device, and particularly relates to a silicon interposer built-in wiring substrate which can correspond to the mounting of a high-performance semiconductor chip and a manufacturing method thereof and a semiconductor device.
2. Description of the Related Art
In the prior art, there has been a semiconductor device in which a semiconductor chip such as a CPU is mounted on a wiring substrate therein. As the wiring substrate on which the semiconductor chip is mounted, a build-up wiring board is generally used in which wirings are formed into multiple layers at fine pitches.
In recent years, connection electrodes have come to have smaller pitches, accompanying with a further higher performance of a semiconductor chip. Since there is a limitation to make the pitch finer between wirings of a build-up wiring board, it has begun to be difficult to directly mount such a semiconductor chip on the build-up wiring board. As a countermeasure to that difficulty, a method has been proposed in which a semiconductor chip is connected to a build-up wiring board via a silicon interposer therebetween, the silicon interposer having fine wirings which enable electrical connection between the upper and lower sides.
Patent Literature 1 (Japanese Patent Application Laid-Open No. 2001-102479) describes that, in order to decrease the number of wiring layers in a semiconductor chip, a function of wirings in the semiconductor chip is transferred to an interposer, and the semiconductor chip is mounted on a wiring substrate via the interposer therebetween.
Patent Literature 2 (Japanese Patent Application Laid-Open No. 2004-273938) describes that an interposer substrate is disposed between an upper device unit and a lower device unit. In the upper device unit, a semiconductor element is mounted on a first wiring substrate having an external connection terminal. In the lower device unit, a semiconductor element is mounted on a second wiring substrate having a connection electrode.
As described above, with a higher performance of a semiconductor chip, wirings in a build-up wiring board further need to be formed into multiple layers at fine pitches, and moreover a silicon interposer needs to be introduced. As a result, the increase in cost for a semiconductor device and the decrease in the yield thereof tend to occur.
For example, at a time of pulling-out a wiring from a through-hole land of a build-up wiring board so as to dispose an interposer pad to which a silicon interposer is connected, there is a case where the through-hole land becomes an obstacle in the middle of pulling-out the wiring, making it impossible to pull-out the wiring. Thus, the number of wiring layers of the build-up wiring board needs to be increased to solve the problem.
At this time, in the case of the build-up wiring board of the prior art, even when the problem can be solved by adding a wiring only on one surface side, it is necessary to symmetrically form the wirings on both surface sides of the core substrate so as to prevent an occurrence of warping, as the result, a problem in which it costs unnecessary expenses is occurs.
As described above, in the case of the build-up wiring board of the prior art, to form the unnecessary wirings is necessary upon making it correspond to the higher performance of a semiconductor chip. As a result, the number of wiring layers becomes enormous in some cases, leading to concerns of the increase in cost and the decrease in yield. Furthermore, when the silicon interposer is connected to the top of the build-up wiring board to construct an interposer built-in wiring substrate, the structure have a high reliability is required.